RISC-V: They Should Have Known Better

Dmitry.GR has expressed his distaste for RISC-V, an open-source instruction set architecture, citing its inability to be the best for all use cases. He argues that RISC-V fans believe it will dominate all supercomputers and tiny microcontroller use cases, which is impossible due to the vastly different design requirements for high-end CPUs and small cost-saving microcontrollers. The key issue lies in the design choices that impact the CPU architecture itself, making it challenging for RISC-V to excel in both high-end and low-end applications. Dmitry.GR is certain that RISC-V will eventually own the cheap single-use microcontroller space, but not due to its ISA design, rather despite it, as it will improve upon the existing 8051 architecture.

The most significant consequence of RISC-V's design is its poor performance in interrupt handling, a critical aspect of cheap microcontroller cores. These cores are used to interface with and reconfigure hardware blocks in larger chips, such as MP3 players, SD cards, or USB sticks. In these scenarios, interrupt latency and size are crucial, and RISC-V's design falls short. The lack of a spec-compliant way to handle interrupts without the Zicsr extension is a significant limitation, forcing developers to use alternative methods that increase interrupt overhead. In contrast, competing cores like the Cortex-M0 can handle interrupts much faster, with a 15-cycle entry and 12-cycle exit, making RISC-V's 44-cycle overhead seem excessive. Even the RV32E variant, with half as many registers, still has an interrupt overhead of 38 cycles, which is over a third more than the Cortex-M0.

The implications of RISC-V's design limitations are far-reaching, affecting not only the performance of cheap microcontroller cores but also the overall viability of the ISA in various applications. The existence of extensions like CLIC and proprietary "fast IRQ" / auto-stacking extensions is seen as an indictment of the base ISA, highlighting its shortcomings. As RISC-V continues to gain traction, its inability to excel in specific use cases may hinder its adoption, particularly in areas where interrupt handling is critical. Dmitry.GR's critique serves as a warning, emphasizing the importance of understanding the trade-offs and limitations of RISC-V's design. While RISC-V may still find success in certain niches, its failure to address fundamental issues like interrupt handling may ultimately limit its potential as a versatile and widely adopted ISA.

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